View MSC23837A_46848.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Semiconductor MSC23837A-xxBS18/DS18
Semiconductor 8,388,608-Word 36-Bit DRAM MODULE : FAST PAGE MODE TYPE
MSC23837A-xxBS18/DS18
DESCRIPTION
The Oki MSC23837A-xxBS18/DS18 is a fully decoded 8,388,608-word 36-bit CMOS dynamic random access memory composed of eighteen 16-Mb DRAMs (4M 4) in SOJ packages mounted with decoupling capacitors on a 72-pin glass epoxy SIMM Package. This module is generally used for memory expansion in parity applications such as workstations.
FEATURES
* 8,388,608-word 36-bit (ECC) organization * 72-pin SIMM MSC23837A-xxBS18 : Gold tab MSC23837A-xxDS18 : Solder tab * Single 5 V supply 10% tolerance * Input : TTL compatible * Output : TTL compatible, 3-state * Refresh : 4096 cycles/64 ms * CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability * Multi-bit test mode capability * Fast Page Mode capability
PRODUCT FAMILY
Family MSC23837A-60BS18/DS18 MSC23837A-70BS18/DS18 Access Time (Max.) tRAC tAA tCAC tOEA 60 ns 30 ns 15 ns 15 ns 70 ns 35 ns 20 ns 20 ns Power Dissipation Cycle Time Operating (Max.) Standby (Max.) (Min.) 110 ns 130 ns 5197.5 mW 4702.5 mW 99 mW
215
MSC23837A-xxBS18/DS18
Semiconductor
PIN CONFIGURATION
MSC23837A-xxBS18/DS18
*1 107.95 0.2 101.19 Typ. (Unit : mm)
9.3 Max.
3.38 0.2 3.18
25.4 0.2
Typ. Typ. 10.16 6.35
1 R1.57 1.27 0.1 6.35 95.25 1.04 Typ.
72
3.5 Min. 6.5 Min. +0.1 1.27 -0.08
2.03 Typ. 6.35 Typ.
*1 The common size difference of the board width 12.5 mm of its height is specified as 0.2. The value above 12.5 mm is specified as 0.5.
Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC PD5 A0 A1 A2 A3
Pin No. Pin Name 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A4 A5 A6 OE DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A7 DQ16 VCC
Pin No. Pin Name 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 A8 A9 NC NC DQ17 DQ18 DQ19 DQ20 VSS CAS0 A10 A11 CAS1 RAS0 RAS1
Pin No. Pin Name 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 DQ21 WE NC DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VCC DQ32
Pin No. Pin Name 61 62 63 64 65 66 67 68 69 70 71 72 DQ33 DQ34 DQ35 NC NC NC PD1 PD2 PD3 PD4 NC VSS
Presence Detect Pins
Pin No. 67 68 69 70 11 Pin Name PD1 PD2 PD3 PD4 PD5 MSC23837A -60BS18/DS18 NC VSS NC NC VSS MSC23837A -70BS18/DS18 NC VSS VSS NC VSS
216
Semiconductor
MSC23837A-xxBS18/DS18
BLOCK DIAGRAM
A0 - A11 RAS0 CAS0 WE OE A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VSS VCC A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS A0 - A11 DQ RAS DQ CAS DQ WE DQ OE VSS VCC RAS1 CAS1 VCC VSS C1 C18 DQ0 DQ1 DQ2 DQ3 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS A0 - A11 DQ RAS DQ CAS DQ DQ WE OE VCC VSS DQ20 DQ21 DQ22 DQ23 DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC DQ A0 - A11 RAS DQ CAS DQ WE DQ OE VSS VCC
DQ4 DQ5 DQ6 DQ7
DQ24 DQ25 DQ26 DQ27
DQ8 DQ9 DQ10 DQ11
DQ28 DQ29 DQ30 DQ31
DQ12 DQ13 DQ14 DQ15
DQ32 DQ33 DQ34 DQ35
DQ16 DQ17 DQ18 DQ19
217
MSC23837A-xxBS18/DS18
Semiconductor
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Voltage VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD Topr Tstg Rating -1.0 to 7.0 -1.0 to 7.0 50 18 0 to 70 -40 to 125 Unit V V mA W C C
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -1.0 Typ. 5.0 0 -- -- Max. 5.5 0 6.5 0.8 (Ta = 0C to 70C) Unit V V V V
Capacitance
Parameter Input Capacitance (A0 - A11) Input Capacitance (RAS0, RAS1, CAS0, CAS1) Input Capacitance (WE, OE) I/O Capacitance (DQ0 - DQ35) Symbol CIN1 CIN2 CIN3 CDQ Typ. -- -- -- -- Max. 122 73 140 26
(Ta = 25C, f = 1 MHz) Unit pF pF pF pF
Note : Capacitance measured with Boonton Meter.
218
Semiconductor DC Characteristics
MSC23837A Parameter
Symbol
MSC23837A-xxBS18/DS18
(VCC = 5 V 10%, Ta = 0C to 70C) MSC23837A -70BS18/DS18 Min. -180 Max. 180 A Unit Note Condition 0 V VI 6.5 V; -60BS18/DS18 Min. Max. 180
Input Leakage Current
ILI
All other pins not under test = 0 V DOUT disable 0 V VO 5.5 V IOH = -5.0 mA IOL = 4.2 mA RAS, CAS cycling, tRC = Min. RAS, CAS = VIH
-180
Output Leakage Current Output High Voltage Output Low Voltage Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode)
ILO VOH VOL ICC1
-20 2.4 0 -- -- --
20 VCC 0.4 945 36 18
-20 2.4 0 -- -- --
20 VCC 0.4 855 36 18
A V V mA 1, 2 mA mA 1 1
ICC2
RAS, CAS VCC -0.2 V RAS cycling,
ICC3
CAS = VIH, tRC = Min. RAS cycling,
--
945
--
855
mA 1, 2
ICC6
CAS before RAS, tRC = Min. RAS = VIL,
--
945
--
855
mA 1, 2
ICC7
CAS cycling, tPC = Min.
--
855
--
765
mA 1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition. 2. Address can be changed once or less while RAS=VIL. 3. Address can be changed once or less while CAS=VIH.
219
MSC23837A-xxBS18/DS18
Semiconductor
AC Characteristics (1/2)
(VCC = 5 V 10%, Ta = 0C to 70C) MSC23837A MSC23837A -70BS18/DS18 Min. 130 185 45 100 -- -- -- -- -- 0 0 0 3 -- 50 70 70 20 10 10 20 70 10 40 20 15 0 10 0 15 55 35 Max. -- -- -- -- 70 20 35 40 20 -- 20 20 50 64 -- 10k 100k -- -- -- 10k -- -- -- 50 35 -- -- -- -- -- --
Symbol
Note 1,2,3,11,12 Unit Note ns ns ns ns ns 4, 5, 6 ns 4, 5 ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 4, 6 4 4 4 7 7 3
Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time
-60BS18/DS18 Min. Max. -- -- -- -- 60 15 30 35 15 -- 15 15 50 64 -- 10k 100k -- -- -- 10k -- -- -- 45 30 -- -- -- -- -- -- 110 155 40 85 -- -- -- -- -- 0 0 0 3 -- 40 60 60 15 10 10 15 60 10 35 20 15 0 10 0 15 50 30
tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL
220
Semiconductor
MSC23837A-xxBS18/DS18
AC Characteristics (2/2)
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1,2,3,11,12 MSC23837A MSC23837A -70BS18/DS18 Min. Max. 0 0 0 0 15 55 10 20 20 20 0 15 55 20 50 65 100 70 10 10 20 10 10 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 10 10 8 8 9
Symbol
Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge to WE Delay Time
-60BS18/DS18 Min. Max. 0 0 0 0 10 45 10 15 15 15 0 15 50 15 40 55 85 60 10 10 20 10 10 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tRCS tRCH tRRH tWCS tWCH tWCR tWP tOEH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD
CAS Active Delay Time from RAS Precharge tRPC RAS to CAS Set-up Time (CAS before RAS) tCSR RAS to CAS Hold Time (CAS before RAS) tCHR WE to RAS Precharge Time (CAS before RAS) tWRP WE Hold Time from RAS (CAS before RAS) tWRH RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tWTS tWTH
221
MSC23837A-xxBS18/DS18
Semiconductor
Notes:
1. A start-up delay of 200 s is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. When using the internal refresh counter, a minimum of eight CAS before RAS initialization cycles is required. 2. AC mesurement assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times are measured between VIH and VIL. 4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves an open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.) the cycle is an early write cycle and the data output pin will remain in a high impedance state throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), the cycle is a read modify write cycle and the data output pin will contain data read from the selected cell. If neither conditions is satisfied, the data output logic state (at access time) is undefined. 10. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in an OE control write cycle or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 4-bit parallel test function. CA0 and CA1 are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. The 8M 36 module can be tested as a 2M 36 module in this test mode. 12. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values.
See ADDENDUM E for AC Timing Waveforms
222

▲Up To Search▲

Price & Availability of MSC23837A

	To Download MSC23837A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .